12-15 April 2021
CET timezone

All PATC Courses at BSC do not charge fees.

Antonio Peña, Computer Sciences Senior Researcher, Accelerators and Communications for High Performance Computing, BSC


The aim of this course is to provide students with knowledge and hands-on experience in developing applications software for processors with massively parallel computing resources. In general, we refer to a processor as massively parallel if it has the ability to complete more than 64 arithmetic operations per clock cycle. Many commercial offerings from NVIDIA, AMD, and Intel already offer such levels of concurrency. Effectively programming these processors will require in-depth knowledge about parallel programming principles, as well as the parallelism models, communication models, and resource limitations of these processors.


The target audiences of the course are students who want to develop exciting applications for these processors, as well as those who want to develop programming tools and future implementations for these processors.

Level: INTERMEDIATE: for trainees with some theoretical and practical knowledge; those who finished the beginners course

ADVANCED: for trainees able to work independently and requiring guidance for solving complex problems

Prerequisites: Basics of C programming and concepts of parallel processing will help, but are not critical to follow the lectures.

Further information:

In the context of virtual meetings, the Organiser may facilitate live webstreaming and audio recording. You have the option to opt out of inclusion in recordings by contacting our Education&Training team.

CONTACT US for further details about MSc, PhD, Post Doc studies, exchanges and collaboration in education and training with BSC.
For further details about Postgraduate Studies in UPC - Barcelona School of Informatics (FiB), visit the website

Sponsors: BSC and PRACE 6IP project are funding the PATC @ BSC training events.
If you want to learn more about PRACE Project, visit the website.

Day 1    
9:15 The Basics Antonio J. Peña
10:45 Coffee Break  
11:15 Parallelism Model Simón García de Gonzalo
13:00 Lunch Break  
14:00 Memory and Data Locality Simón García de Gonzalo
15:45 Coffee Break  
16:15 Hands-on labs Marc Jordà
18:00 Adjourn  
Day 2    
9:00 Efficiency and Performance Considerations Marc Jordà
10:45 Coffee Break  
11:15 Atomics and Histogramming, Reductions Simón García de Gonzalo
13:00 Lunch Break  
14:00 Architectural Considerations Siddharth Rai
14:45 Efficient Host-Device Data Transfers Siddharth Rai
15:45 Coffee Break  
16:15 Hands-on labs Marc Jordà
18:00 Adjourn  
Day 3    
9:00 OpenACC and Other Approaches to GPU Computing Orestis Korakitis
10:45 Coffee Break  
11:15 Latest Architecture & CUDA Features Marc Jordà
13:00 Lunch Break  
14:00 Hands-on labs Marc Jordà
18:00 Adjourn  
Day 4    
9:00 Hands-on labs Marc Jordà
10:45 Coffee Break  
11:15 Hands-on labs Marc Jordà
13:00 Adjourn  

End of Course



For further details and practical info such as local transport and venue please visit the local course pages for PATC@BSC: http://www.bsc.es/patc