17TH VI-HPS Tuning Workshop @ HLRS

Big seminar room (HLRS (Höchstleistungsrechenzentrum Stuttgart))

Big seminar room

HLRS (Höchstleistungsrechenzentrum Stuttgart)

University of Stuttgart, Allmandring 30, D-70569 Stuttgart Germany


This workshop organized by VI-HPS for the GermanPrace Advanced Training Centre hosted by HLRS will:
  • give an overview of the VI-HPS programming tools suite
  • explain the functionality of individual tools, and how to use them effectively
  • offer hands-on experience and expert assistance using the tools 

Programme Overview

Presentations and hands-on sessions are planned on the following topics:
  • Setting up, welcome and introduction
  • LWM2 lightweight monitoring
  • Score-P instrumentation and measurement
  • Scalasca automated trace analysis
  • Vampir interactive trace analysis
  • Periscope automated performance analysis
  • Paraver trace analysis and performance prediction
  • MAQAO performance analysis & optimization
  • MUST runtime error detection for MPI
  • MAP profiling and performance reports
  • Cray performance analysis tools

A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

The workshop will be held in English and run from 09:00 to not later than 18:00 each day, with breaks for lunch and refreshments. For participants from public research institutions in PRACE countries, the course fee is sponsored through the PRACE PATC program. All participants are responsible for their own travel and accommodation.
Classroom capacity is limited, therefore priority will be given to applicants with parallel codes already running on the workshop computer system (Hornet), and those bringing codes from similar Cray systems to work on. Participants are therefore encouraged to prepare their own MPI, OpenMP and hybrid MPI+OpenMP parallel application codes for analysis.

Hardware and Software Platforms

Hornet: 21-cabinet Cray Cascade XC40 system:
  • 3944 compute nodes each with two Intel Xeon E5-2680v3 'Haswell' processors (2.50GHz, 12 cores per processor, 2 hardware threads per core) and 128 GB memory
  • network: Aries dragonfly interconnect
  • software: Cray lightweight CNL kernel & MPI; Cray CCE, GCC and Intel compilers
The local HPC system Hornet is the primary platform for the workshop and will be used for the hands-on exercises. Course accounts will be provided during the workshop to participants without existing accounts. Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited and participants are expected to already possess user accounts on non-local systems. Regardless of whichever systems they intend to use, participants should be familiar with the relevant procedures for compiling and running their parallel applications (via batch queues where appropriate).

The programme in detail can be found on the VI-HPS training web site.

Local organizer: Rolf Rabenseifner, Gabi Kallenberger
The agenda of this meeting is empty