PRACE code porting workshop in Cracow, Poland

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Description

This workshop will be focused on some specific aspects of NEC and BlueGene HPC solutions by renowned experts in the area. It is addressed to researchers and students from Europe who are interested in the state of the art HPC infrastructures and practical introduction into porting applications to them. The maximum number of participants in this event is limited to 50 people.

The workshop attendees will have a chance to have a hands on experience with programming on HPC systems including BlueGene/P at FZJ and NEC at HRLS and the attendees will recieve accounts on these machines which will be valid during the workshop sessions. The particpants will have a chance to get experience with code porting on real machines during the workshops sessions:

  • IBM BlueGene/P in FZJ Julich - The IBM BlueGene/P (BG/P) installation at the Forschungszentrum Julich (FZJ), named jugene, is one of the six PRACE petascale prototypes. As this architecture significantly differs from general purpose architectures, optimal code porting is a challenging task. The aim of this workshop's part will be to introduce the BG/P architecture, the main features and the usage model at FZJ. To illustrate the presented topics, the participants will be able to use jugene during the workshop in the hands-on sessions. The main focus in these sessions will be the general usage, utilization of the double-hummer unit, i.e. single core performance, as well as the 3D torus network.
  • NEC SX-9 in HRLS Stuttgart - The NEC SX9 is the latest incarnation of the NEC SX series and is the only remaining traditional large vector system for HPC on the market today. It provides an amazing system with important features. These features are briefly presented to provide a basic impression of this system. The participants will have a chance to work on this powerful vector processor achieving floating point peak performance of 102.4 GFLOPs. As this is a unique feature in this system and yields the largest differences to more common hardware architectures.

Presenters - Lukas Arnold and Kamil Iskra

Slides