Hardware technologies in High Performance Computing are continuously undergoing major changes and rapidly increasing performance capabilities, but the software and the underlying code legacy is often left unchanged or even neglected. This leads to performance gaps and underutilized hardware assets. In this workshop you will learn from experts how to tackle these issues and make sure your code is ready to perform on tomorrow’s HPC processing technologies.

The aims of this course are:

1) To provide the attendants with an overview of the current and next Intel Xeon and Xeon Phi architectures and
2) To teach the tools in order to get from those architectures  the maximum in terms of performance.

Target Audience

HPC users and developers

Topics

Compilers, profilers, tools and techniques for optimization.

Prerequisites

C/Fortran, MPI, OpenMP

Grant
The lunch for the two days will be offered to all the participants and some grants are available. The only requirement to be eligible is to be not funded by your institution to attend the course and to work or live in an institute outside the Bologna area. The grant  will be 200 euros for students working and living outside Italy and 100 euros for students working and living in Italy. Some documentation will be required and the grant will be paid only after a certified presence of minimum 80% of the lectures.

Further information about how to request the grant, will be provided at the confirmation of the course: about 3 weeks before the starting date.

 

 

Starts
Ends
CET
CINECA - BOLOGNA
Via Magnanelli 6/3 40033 Casalecchio di Reno (Bologna) Italy

A maximum number of 24 students will be accepted.

PLEASE NOTE: SECRETARY RESERVES THE RIGHT TO CLOSE BEFORE THE DEADLINE THE SUBCRIPTIONS, IF REACHED THE MAXIMUM NUMBER OF SEATS AVAILABLE.