Intel, Bayncore and STFC/ Daresbury Laboratory, together with the National Center for Supercomputing Applications (NCSA-BG), announces training course “Enabling Software Scalability and Performance on Intel Xeon and Xeon Phi Platforms”, which will take place on December 15-17 in Sofia at the Institute of Information and Communication Technologies, Bulgarian Academy of Sciences.
This PRACE Training Course is the second part of the training school “Code Modernisation for Intel Multi Core and Xeon Phi Architectures”, conduct through April 25-28 in Sofia.
In order to gain the maximal possible performance of the massively parallel heterogeneous systems and to ensure high scalability of the applied programs, the software engineers need to have in-depth knowledge of translators, libraries, tools and utilities.
The course will focus on
- Tips and tricks to warrant parallel efficiency on Xeon Phi - Multi-threading mode and common MPI/OpenMP techniques;
- Techniques and facilities for overlapping computations and communications;
- Minimising time to access and exchange of data between XeonPhi and main memory;
- Techniques and tools for minimisation at time for communications between Xeon Phi cores;
- One Sided Programming and Partitioned Global Address Space (PGAS) with MPI.
Level: The course is designed for software engineers with good proficiency in C/C++ and Python, with experience in parallel programming on Intel architectures in Linux environment.
Lecturers and Organisers:
 |
 |
 |
 |
- Bayncore: Stephen Blair–Chappell, Former Technical Consulting Engineer at Intel
- Intel: Victor Gamayunov, Technical Consulting Engineer at Intel
- Daresbury Laboratory:
- Dr. Ilian Todorov, Group Lead SCD/Hartree Centre
- Dr. Alin-Marin Elena, HPC Specialist and Consultant at SCD/Hartree Centre
Contact person: Mariya Durchova, e-mail: mabs@parallel.bas.bg
Disclaimer: Some of the material used in this training event has been prepared by Intel, Bayncore and STFC/ Daresbury Laboratory HPC Specialists. The training event is financially supported in part by the PRACE-4IP project funded by the EU’s Horizon 2020 research and innovation programme (2014-2020) under grant agreement 653838. The training material prepared by Intel, Bayncore and STFC/Daresbury Laboratory HPC Specialists solely reflects the opinion Intel, Bayncore and STFC/ Daresbury Laboratory HPC Specialists in the context of such training event. Please note that the content of this training material has not been approved by the PRACE Project Partners and therefore does not emanate from them nor should it be considered to reflect their individual or collective opinion.
