The course discusses Intel’s Many Integrated Core (MIC) architecture. It covers various programming and optimisation techniques for Intel Xeon Phi coprocessors. We will mainly focus on the KNC version of the chip, but will also introduce the Knights Landing chip. The hands-on sessions are done on the Intel Xeon Phi based Salomon system at the IT4Innovations National Supercomputing Center.
The topics of the first 1.5 days reach from an introduction about the Intel MIC architecture and various Intel Xeon Phi programming models (Offloading, Native mode, MKL, OpenMP, MPI etc.) to advanced topics about vectorisation and performance optimisation, interleaved with many hands-on sessions on the Intel Xeon Phi based Salomon system at IT4Innovations.
During a plenum session on the last day invited speakers talk about MIC experience and best practice recommendations using Intel Xeon Phi based systems like e.g. Salomon @ IT4Innovations.
The course is developed within the joint German-Czech project CzeBaCCA, as a follow-up of the MIC porogramming workshop of February 2016. A two-day Scientific Workshop "HPC in Atmosphere Modelling and Air Related Environmental Hazards" of this project will take place at IT4Innovations directly after this course, on February 9-10, 2017 - see its web page for details.
The course is a PRACE Advanced Training Center event.
|Tuesday February 7, 2017|
|11:00-12:00||Overview of the Intel MIC architecture and programming models|
|13:00-13:30||Native mode programming|
|13:30-15:30||OpenMP and offloading I|
|16:00-17:00||OpenMP and offloading II|
|Wednesday February 8, 2017|
|11:00-12:00||Vectorisation and Intel Xeon Phi performance optimisation|
Plenum session with invited talks Wednesday February 8, 2017:
Jan Zapletal ( IT4Innovations): Boundary element quadrature schemes for multi- and many-core architectures
|13:45-14:15||Jiri Jaros (VUT Brno): Acceleration of the k-Wave toolbox on Xeon Phi|
|14:15-15:00||Lukasz Szustak, Roman Wyrzykowski (TU Czestochowa): Exploring the impact of Intel MIC and Intel CPU architectures on accelerating scientific applications|
|15:30-16:15||Michal Merta (IT4Innovations): Acceleration of the ESPRESO domain decomposition library|
|16:15-17:00||Milan Jaros (IT4Innovations): Acceleration of Blender Cycles Render Engine using Intel® Xeon Phi™|
Momme Allalen received his Ph.D in theoretical Physics from the University of Osnabrück in 2006. He worked in the field of molecular magnetics through modelling techniques such as the exact numerical diagonalisation of the Heisenberg model. He joined the Leibniz Computing Centre (LRZ) in 2007 working in the High Performance Computing group. His tasks include user support, optimisation and parallelisation of scientific application codes, and benchmarking for characterising and evaluating the performance of high-end supercomputers. His research interests are various aspects of parallel computing and new programming languages and paradigms.
Branislav Jansik has obtained his PhD in computational chemistry at Royal Institute of Technology, Sweden in 2004. He took postdoctoral position at IPCF, Consiglio Niazionale delle Ricerche, Italy, to carry on development and applications of high performance computational methods for molecular optical properties. Since 2006 he worked on development of highly parallel optimization methods in the domain of electronic structure theory at Aarhus University, Denmark. In 2012 he joined IT4Innovations, the Czech national supercomputing center as a head of supercomputing services. He published over 35 papers and co-authored the DALTON electronic structure theory code.
Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is responsible for HPC and PATC (PRACE Advanced Training Centre) courses at LRZ, new programming languages and the Intel Xeon Phi based system SuperMIC. Within PRACE-4IP he took over the leadership to create Best Practice Guides for new architectures and systems.