26-28 June 2017
CET timezone


The course discusses Intel’s Many Integrated Core (MIC) architecture and programming models for Intel Xeon Phi co/processors in order to enable programmers to achieve good performance of their applications. The course will mainly concentrate on techniques relevant for Knights Landing (KNL) based systems, like the future KNL cluster CoolMUC3 to be installed at LRZ, soon.

The workshop covers a wide range of topics from the description of the hardware of the Intel Xeon Phi co-/processors through information about the basic programming models as well as information about vectorisation and MCDRAM usage up to tools and strategies how to analyse and improve the performance of applications.

The workshop will include both theoretical and practical hands-on sessions.

There will also be a session with invited talks by speakers from Intel, IPCC@LRZ, IPCC@TUM, IPCC@IT4Innovations, IPP, RRZE and the University of Regensburg about Intel Xeon Phi - especially KNL - experience and best practice recommendations.

The course is developed within the joint German-Czech Republic project CzeBaCCA. A workshop on "HPC for natural hazard assessment and disaster mitigation" of this project will take place at LRZ directly after this course (see https://www.lrz.de/services/compute/courses/2017-06-28_hnha1s17/).

Please bring your own laptop (with an ssh client installed) for the hands-on sessions!


Figure: Participants of the MIC Workshop 2016

Preliminary schedule

Monday, June 26, 2017, Kursraum 2, H.U.010 (course room)

  • 09:00-10:00 Welcome & Introduction (Weinberg)
  • 10:00-10:30 Overview of the Intel MIC architecture (Allalen)
  • 10:30-11:00 Coffee break
  • 11:00-11:30 Overview of the Intel MIC programming models (Allalen)
  • 11:30-12:00 Native mode KNC and KNL programming (Allalen)
  • 12:00-13:00 Lunch break
  • 13:00-13:45 KNL Memory Modes and Cluster Modes, MCDRAM (Weinberg)
  • 13:45:15:30 Offloading (Weinberg)
  • 15:30-16:00 Coffee break
  • 16:00-17:00 MKL (Allalen)

Tuesday, June 27, 2017, Kursraum 2, H.U.010 (course room)

  • 09:00-10:30 Vectorisation and Intel Xeon Phi performance optimisation (Allalen)
  • 10:30-11:00 Coffee break
  • 11:00-12:00 Guided SuperMUC/MIC Tour (Weinberg/Allalen)
  • 12:00-13:00 Lunch break
  • 13:00-15:30 KNL code optimisation process (Baruffa)
  • 15:30-16:00 Coffee Break
  • 16:00-17:00 Profiling tools: Intel Advisor (Baruffa)
  • 18:00 - open end at GARNIX  https://www.garnix-festival.de/

Wednesday, June 28, 2017, 09:00-12:00, Hörsaal, H.E.009 (Lecture Hall)

  • 09:00-10:30 Many-core Programming with OpenMP 4.x (Michael Klemm, Intel)
  • 10:30-10:45 Coffee Break
  • 10:45-12:00 Advanced KNL programming techniques (Intrinsics, Assembler, AVX-512,...) (Jan Eitzinger, RRZE)

Wednesday, June  28,  2017, 13:00-18:00, Hörsaal, H.E.009 (Lecture Hall)

Plenum session with invited talks on MIC experience and best practice recommendations
(joint session with the Scientific Workshop "HPC for natural hazard assessment and disaster mitigation"), public session

  • 13:00-13:30 Luigi Iapichino, IPCC@LRZ: "Performance Optimization of Smoothed Particle Hydrodynamics and Experiences on Many-Core Architectures"
  • 13:30-14:00 Michael Bader/Carsten Uphoff, IPCC@TUM: "Extreme-scale Multi-physics Simulation of the 2004 Sumatra Earthquake"
  • 14:00-14:30 Vit Vondrak/Branislav Jansik, IPCC@IT4I: "Development of Intel Xeon Phi Accelerated Algorithms and Applications at IT4I"
  • 14:30-15:00 Michael Klemm, Intel: "Application Show Cases on Intel® Xeon Phi™ Processors"
  • 15:00-15:30 Coffee Break
  • 15:30-16:00 Jan Eitzinger, RRZE: "Evaluation of Intel Xeon Phi "Knights Landing":  Initial impressions and benchmarking results"
  • 16:00-16:30 Piotr Korcyl, University of Regensburg: "Lattice Quantum Chromodynamics on the MIC architectures"
  • 16:30-17:00 Nils Moschüring, IPP: "The experience of the HLST on Europes biggest KNL cluster"
  • 17:00-17:30 Andreas Marek, Max Planck Computing and Data Facility (MPCDF), "Porting  the ELPA library to the KNL architecture"
  • 17:30-18:00 Q&A, Wrap-up

The course material is developed within PRACE and the joint German-Czech Republic project CzeBaCCA.

The course is a PRACE Advanced Training Center event.

A social event for participant and instructor networking is planned for the evening on Tuesday, 27 June.

About the tutors

Dr. Momme Allalen received his Ph.D in theoretical Physics from the University of Osnabrück in 2006. He worked in the field of molecular magnetics through modelling techniques such as the exact numerical diagonalisation of the Heisenberg model. He joined the Leibniz Computing Centre (LRZ) in 2007 working in the High Performance Computing group. His tasks include user support, optimisation and parallelisation of scientific application codes, and benchmarking for characterising and evaluating the performance of high-end supercomputers. His research interests are various aspects of parallel computing and new programming languages and paradigms.

Dr. Fabio Baruffa is HPC Application Specialist at LRZ and member of the Intel Parallel Computing Center (IPCC). He was working as HPC researcher at Max-Planck (MPCDF), Jülich Research Center and Cineca where he was involved in HPC software development. His main research interests are in the area of computational methods and optimizations for HPC systems. He holds a PhD in Physics from University of Regensburg for his research in the area of spintronics.

Dr.-Ing. Jan Eitzinger (RRZE) (formerly Treibig) holds a PhD in Computer Science from the University of Erlangen. He is now a postdoctoral researcher in the HPC Services group at Erlangen Regional Computing Center (RRZE). His current research revolves around architecture-specific and low-level optimization for current processor architectures, performance modeling on processor and system levels, and programming tools. He is the developer of LIKWID, a collection of lightweight performance tools. In his daily work he is involved in all aspects of user support in High Performance Computing: training, code parallelization, profiling and optimization, and the evaluation of novel computer architectures.

Dr.-Ing. Michael Klemm (Intel Corp.) obtained an M.Sc. in Computer Science in 2003 and received a Doctor of Engineering degree (Dr.-Ing.) from the Friedrich-Alexander-University Erlangen-Nuremberg, Germany, in 2008. Michael Klemm works in the Developer Relations Division at Intel in Germany and his areas of interest include compiler construction, design of programming languages, parallel programming, and performance analysis and tuning. Michael Klemm joined the OpenMP organization in 2009 and was appointed CEO of the OpenMP ARB in 2016.

Dr. Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is responsible for HPC and PATC (PRACE Advanced Training Centre) courses at LRZ, new programming languages and the Intel Xeon Phi based system SuperMIC. Within PRACE-4IP he took over the leadership to create Best Practice Guides for new architectures and systems.



Starts 26 Jun 2017 09:00
Ends 28 Jun 2017 18:00


Good working knowledge of at least one of the standard HPC languages: C, C++ or Fortran. Basic OpenMP and MPI knowledge useful. Please bring your own laptop for the hands-on sessions.
Language: English
Further information: Travel info, hotel info, course page at LRZ
Registration: Via https://events.prace-ri.eu/event/609/registration/register


Volker Weinberg, Momme Allalen, Fabio Baruffa (Leibniz Supercomputing Centre), Michael Klemm (Intel), invited speakers