3-4 December 2018
Europe/London timezone

A number of manufacturers have recently started to produce high performance, multicore CPUs based on the ARM64 architecture. This hands-on workshop is aimed at helping users to port HPC codes to ARM64 processors.

Although ARM64 is already supported by a number of compiler suites including GNU, ARM and Cray, many users may only have experience in compiling for the Intel x86
architecture so some changes to the build procedure may be required. In particular, the compilation options required for best performance may be different.

This 2-day hands-on workshop, delivered by staff from ARM and EPCC, will cover the ARM64 architecture, compilers and libraries. Access will be provided to the Tier2 GW4 Isambard system, based on Cavium ThunderX2 CPUs, for all practical exercises.

Although test codes will be provided for the hands-on exercises, all attendees are encouraged to bring their own applications to work on during the practical sessions.


Outline timetable

Monday 3rd December

  • 09:30 - Registration
  • 10:00 - Welcome and Introduction
  • 10:10 - Introduction to the Arm architecture
  • 10:30 - Arm in HPC - Hardware and Ecosystem
  • 11:00 - The Catalyst project
  • 11:30 - Break
  • 11:45 - Compilers and Tools
  • 12:30 - Hands on - Getting started
  • 13:00 - Lunch (not provided)
  • 14:00 - Hands on: Part 1
  • 16:00 - Close

Tuesday 4th December

  • 10:00 - Optimisation for Arm
  • 11:00 - Vectorisation
  • 11:30 - Looking forward - SVE
  • 12:00 - Hands on: Part 2
  • 13:00 - Lunch (not provided)
  • 14:00 - Hands on: Part 2 continued
  • 16:00 - Close



5.02 ICMS
The University of Edinburgh Bayes Centre 47 Potterrow Edinburgh EH8 9BT
This course is part-funded by the PRACE project and is free to all. Please register using the online form. If you have any questions, please consult the course forum page or contact support@archer.ac.uk.