32nd VI-HPS Tuning Workshop (Bristol, England) - PATC course

Date

Wednesday 24th - Friday 26th April 2019

Location

The workshop will take place at the University of Bristol, England.

Co-organizing Institutions

Goals

This workshop is organised by VI-HPS for the UK PRACE Advanced Training Centre to:

• give an overview of the VI-HPS programming tools suite
• explain the functionality of individual tools, and how to use them effectively
• offer hands-on experience and expert assistance using the tools

On completion participants should be familiar with common performance analysis and diagnosis techniques and how they can be employed in practice (on a range of HPC systems). Those who prepared their own application test cases will have been coached in the tuning of their measurement and analysis, and provided optimization suggestions.

Programme Overview

Presentations and hands-on sessions are on the following topics:

• BSC tools for trace analysis and performance prediction
• Score-P instrumentation and measurement
• Scalasca automated trace analysis
• TAU performance system

A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

The workshop will be held in English and run from 09:00 to not later than 17:00 each day, with breaks for lunch and refreshments. There is no fee for participation, however, participants are responsible for their own travel and accommodation.

Classroom capacity is limited, therefore priority will be given to applicants with MPI, OpenMP and hybrid OpenMP+MPI parallel codes already running on the workshop computer systems, and those bringing codes from similar systems to work on. Attendees will need to bring their own notebook computers (with SSH and X11 configured) and use (eduroam) wifi to connect to the workshop computer systems.

Outline

The workshop introduces tools that provide a practical basis for portable performance analysis of parallel application execution, covering both profiling and tracing. It will be delivered as a series of presentations with associated hands-on practical exercises using the ARM-based Isambard Cray XC50 computer.

While analysis of provided example codes will be used to guide the class through the relevant steps and familiarise with usage of the tools, coaching will also be available to assist participants to analyse their own parallel application codes and may suggest opportunities for improving their execution performance and scalability.

Programme (preliminary)

Hardware and Software Platforms

Isambard: Cray XC50 with 164 dual Marvell ThunderX2 32-core 2.1 GHz nodes (64-bit ARMv8-A cores) with 256GB DRAM and Aries dragonfly interconnect, Cray MPI, Cray, GCC & ARM toolchains. Training accounts will be provided!

ARCHER: Cray XC30 with 3008 compute nodes consisting of two 12-core Intel E5-2697 (IvyBridge) processors sharing 64GB (or 128GB) of NUMA memory, Aries dragonfly interconnect, Cray MPI, Cray, GCC & Intel compilers, PBS Pro job management system. Training accounts will be provided!

Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited. Participants are expected to already possess user accounts on non-local systems they intend to use, and should be familiar with the procedures for compiling and running parallel applications.

Registration

Please register via the Registration tab on this page.

Local organisers information page.